SR Nor Latch cONversion

Discussion in 'Silicon (v)Alley' started by Novek, May 16, 2011.

  1. Does anyone know what inputs go where to make a SR Nor Latch stable at SET?

    Im trying to go step by step in making it go from SET to RESET. I went from RESET to SET using a SR NAND latch by labeling:

    S 1 Q=0

    R 0 Q/=1

    From here I introduced a "0" into the "outer" input of the "upper" gate and it eventually looked like this:

    S 1 Q=1

    R 1 Q/=0

    The only difference between the two is the switching of the inner inputs from "1, 0" to "0, 1".

    I cant seem to find the right inputs to make a smooth transition from "SET" TO "RESET" in a SR Nor Latch. Here is a pic. Just needs some numbers plugged into it:

  2. Basically a high on S and a low on R at the inputs will give you the Set condition at the output.

    A low on S and a high on R at the inputs will give you the reset condition at the output.

    Attached Files:

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